Tray Mga Flip Flop

Mga Resulta: 9
Pumili Larawan # ng Piyesa
 Mfr.
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Dami RoHS ECAD Model Uri ng Logic
Logic Family
Dami ng Circuit
Uri ng Output
Package / Case
Uri ng Input
Polarity
Propagation Delay Time
Mataas na Antas na Output Current
Mababang Antas na Output Current
Supply Voltage - Min
Supply Voltage - Max
Isitilo ng Mounting
Minimum na Operating Temperature
Maximum na Operating Temperature
Packaging
onsemi Flip Flops 3.3V/5V ECL 6-Bit Diff w/Master Reset
Datasheet
119May Stock
Min.: 1
Mult.: 1

Differential Register 10 1 Circuit Differential LQFP-32 Differential Inverting/Non-Inverting 0.55 ns - 50 mA 50 mA - 3 V 5.5 V SMD/SMT - 40 C + 85 C Tray

onsemi Flip Flops 3.3V/5V ECL Quad D-Type
Datasheet
87May Stock
Min.: 1
Mult.: 1

Flip-Flop 10 4 Circuit Differential LQFP-32 Single-Ended Inverting/Non-Inverting 0.6 ns - 3 V 5.5 V SMD/SMT - 40 C + 85 C Tray
onsemi Flip Flops 3.3V/5V ECL Quad D-Type
Datasheet
275May Stock
500Inaasahan 8/25/2026
Min.: 1
Mult.: 1
Max.: 110

Flip-Flop 100 4 Circuit Differential LQFP-32 Single-Ended Inverting/Non-Inverting 0.6 ns - 3 V 5.5 V SMD/SMT - 40 C + 85 C Tray

onsemi Flip Flops 3.3V/5V ECL 6-Bit Diff w/Master Reset
Datasheet
250Inaasahan 8/26/2026
Min.: 1
Mult.: 1

Differential Register 100 1 Circuit Differential LQFP-32 Differential Inverting/Non-Inverting 0.55 ns - 50 mA 50 mA - 3 V 5.5 V SMD/SMT - 40 C + 85 C Tray
Texas Instruments Flip Flops DIE SALE
Datasheet
Lead-Time para sa Hindi Naka-stock 26 (na) Linggo
Min.: 100
Mult.: 100

HC CMOS Die CMOS 34 ns - 5.2 mA 5.2 mA 2 V 6 V 0 C + 25 C Tray
Texas Instruments Flip Flops DIE SALE
Datasheet
Lead-Time para sa Hindi Naka-stock 26 (na) Linggo
Min.: 10
Mult.: 10

HC CMOS Die CMOS 34 ns - 5.2 mA 5.2 mA 2 V 6 V 0 C + 25 C Tray
Apogee Semiconductor Flip Flops LEO Dual D Flip-Flops and Registers w/Async Clear A-Grade NiPdAu TSSOP14 JEDEC tray
Datasheet
Lead-Time para sa Hindi Naka-stock 35 (na) Linggo
Min.: 50
Mult.: 50
D Flip-Flop AP54RHC 2 Circuit Complementary TSSOP-14 - 24 mA 24 mA 1.65 VDC 5.5 VDC SMD/SMT - 55 C + 125 C Tray
Apogee Semiconductor Flip Flops LEO Dual D Flip-Flops and Registers w/Async Clear B-Grade NiPdAu TSSOP14 JEDEC tray
Datasheet
Lead-Time para sa Hindi Naka-stock 35 (na) Linggo
Min.: 100
Mult.: 100
D Flip-Flop AP54RHC 2 Circuit Complementary TSSOP-14 - 24 mA 24 mA 1.65 VDC 5.5 VDC SMD/SMT - 55 C + 125 C Tray
Apogee Semiconductor Flip Flops LEO Dual D Flip-Flops and Registers w/Async Clear E-Grade NiPdAu TSSOP14 JEDEC tray
Datasheet
Lead-Time para sa Hindi Naka-stock 35 (na) Linggo
Min.: 250
Mult.: 250
D Flip-Flop AP54RHC 2 Circuit Complementary TSSOP-14 - 24 mA 24 mA 1.65 VDC 5.5 VDC SMD/SMT - 55 C + 125 C Tray