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Analog Devices Inc. ADF4383 Fractional-N Phased-Locked Loops (PLLs)

Analog Devices ADF4383 Fractional-N Phased-Locked Loops (PLLs) are a high-performance, ultra-low jitter, fractional-N phased-locked loop (PLL) with an integrated voltage-controlled oscillator (VCO). These are ideally suited for local oscillator (LO) generation for 5G applications or data converter clock applications. The high-performance PLL has a figure of merit of -239dBc/Hz, low 1/f noise, and a high PFD frequency of 625MHz in integer mode that can achieve ultra-low in-band noise and integrated jitter. The ADF4383 can generate frequencies in a fundamental octave range of 10GHz to 20GHz, eliminating the need for subharmonic filters. The output dividers on the ADF4383 allow a complete output frequency range to be generated from 625MHz to 20GHz.

The ADF4383 automatically aligns its output to the input reference edge for multiple data converter clock applications by including the output divider in the PLL feedback loop. A programmable reference to output delay with < 1ps resolution is provided for applications requiring deterministic delay or delay adjustment capability. The reference to output delay matching across multiple devices and over temperature allows predictable and precise multichip alignment.

The Analog Devices ADF4383 block diagram's simplicity eases development time. It has a simplified serial peripheral interface (SPI) register map, external SYNC input, and repeatable multichip alignment in integer and fractional mode.

Features

  • 10GHz to 20GHz fundamental VCO frequency range
  • VCO phase noise improvement of up to 3dB as compared to ADF4382
  • Integrated RMS jitter at 20GHz = 18fs (integration bandwidth: 100Hz to 100MHz)
  • Integrated RMS jitter at 20GHz = 31fs (ADC SNR method)
  • PLL specifications
    • -239dBc/Hz normalized in-band phase noise floor (integer mode)
    • -287dBc/Hz normalized 1/f phase noise floor
    • 625MHz maximum phase/frequency detector input frequency
    • 4.5GHz reference input frequency
    • -90dBc typical spurious fPFD
  • Fast <2μs VCO calibration time
  • <100μs VCO autocalibration time
  • -156dBc/Hz phase noise floor at 20GHz
  • Reference to output delay specifications
    • 0.06ps/°C propagation delay temperature coefficient
    • <1ps adjustment step size
  • Multichip output phase alignment
  • 3.3V and 5V power supplies
  • ADIsimPLL™ loop filter design tool support
  • 7mm × 7mm, 48-terminal LGA
  • -40°C to +105°C operating temperature

Applications

  • High-performance data converter clocking
  • Wireless infrastructures (MC-GSM, 5G, 6G)
  • Test and measurement

Additional Resources

Functional Block Diagram

Block Diagram - Analog Devices Inc. ADF4383 Fractional-N Phased-Locked Loops (PLLs)
Inilathala: 2025-09-12 | Na-update: 2025-10-01