Intelligent Memory Double Data Rate 2 (DDR2) SDRAM
Intelligent Memory Double Data Rate (DDR2) Synchronous DRAM (SDRAM) are eight-bank devices that achieve high-speed data transfer rates. Interleaving the eight memory banks allows random access operations faster than standard DRAMs. A chip architecture prefetches multiple bits and then synchronizes the output data to a system clock. All control, address, and circuits are synchronized with the positive edge of an externally supplied clock. In a source-synchronous manner, I/Os are synchronized with a pair of bidirectional strobes. A sequential, gapless data rate is possible depending on the device's burst length, CAS latency, and speed grade.Features
- Configurations
- 512Mx4 (8x bank x64Mbit x4)
- 256Mx8 (8x bank x32Mbit x8)
- 128Mx16 (8x bank x16Mbit x16)
- Double data rate clocking timing, 1.8V power supply
- SSTL_18 compatible inputs
- Programmable burst length and CAS latency
- Auto refresh and self-refresh
- Supported OCD (Off-Chip Driver impedance)
- Supported ODT (On-Die Termination)
- High-speed data transfer up to 1066MHz
- 512Mb, 1Gb, and 2Gb are available
- Integrated ECC error correction
- JEDEC compliant FBGA-60 or FBGA-84 packages
- RoHS compliant
Applications
- Commercial
- Industrial
Specifications
- 512Mb, 1Gb, and 2Gb densities
- Maximum speeds
- 400MHz for 512Mb and 2Gb
- 533MHz for 1Gb
- Data rates
- 800Mbps for 512Mb and 2Gb
- 1066Mbps for 1Gb
- 4-bit to 16-bit data bus width
- 1.7V to 1.9V supply voltage range
- 58mA to 90mA maximum supply current
- 1.875ns to 5ns clock cycle time range
- 333MHz to 533MHz system frequency range
- 400ps access time
- Temperature ranges
- 0 to +95°C commercial
- -40°C to +95°C industrial
- -40°C to +105°C high
Simplified State Diagram
Inilathala: 2023-06-29
| Na-update: 2023-07-26
