Texas Instruments OMAP5912 Dual-Core Applications Processor
Texas Instruments OMAP5912 Dual-Core Applications Processor is a highly integrated hardware and software platform designed to meet the application processing needs of next-generation embedded devices. The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The Texas Instruments OMAP5912 dual-core architecture provides benefits of both DSP and reduced instruction set computer (RISC) technologies, incorporating a TMS320C55x DSP core and a high-performance ARM926EJ-S ARM® core.
Features
- Low-power, high-performance CMOS technology
- 0.13µm technology
- 192MHz maximum frequency
- 1.6 ±5% V core voltage
- ARM926EJ-S™ (MPU) core
- Support for 32-bit and 16-bit (Thumb® Mode) instruction sets
- 16Kbyte instruction cache
- 8Kbyte data cache
- Data and program Memory Management Unit (MMU)
- 17-word write buffer
- Two 64-entry Translation Look-Aside Buffers (TLBs) for MMUs
- TMS320C55x™ (C55x™) DSP core
- One/two instructions are executed per cycle
- Dual multipliers (two multiply-accumulates per cycle)
- Two arithmetic/logic units
- Five internal data/operand buses (three read buses and two write buses)
- 32K x 16-bit on-chip dual-access RAM (DARAM) (64Kbytes)
- 48K x 16-bit on-chip single-access RAM (SARAM) (96Kbytes)
- Instruction cache (24Kbytes)
- Video hardware accelerators for DCT, iDCT, pixel interpolation, and motion estimation for video compression
- 250Kbytes of shared internal SRAM
- Memory Traffic Controller (TC)
- 16-Bit EMIFS supports up to 256Mbytes of external memory (i.e., Async. ROM/RAM, NOR/NAND Flash, and Sync. Burst Flash)
- 16-Bit EMIFF to access up to 64Mbytes of SDRAM, mobile SDRAM, or mobile DDR
- DSP Memory Management Unit
- DSP peripherals
- Three 32-bit timers and watchdog timer
- Six-channel DMA controller
- Two multichannel buffered serial ports
- Two multichannel serial interfaces
- MPU peripherals
- Three 32-bit timers and watchdog timer
- USB 1.1 host and client controllers
- USB On-the-Go (OTG) controller
- Three USB ports, one with an integrated transceiver
- Camera interface for parallel CMOS sensors
- Real-Time Clock (RTC)
- Pulse-Width Tone (PWT) interface
- Pulse-Width Light (PWL) interface
- Keyboard matrix interface (6 x 5 or 8 x 8)
- HDQ/1-wire® interface
- Multimedia Card (MMC) and Secure Digital (SD) interface
- Up to 16 MPU general-purpose I/Os
- Two LED Pulse Generators (LPGs)
- ETM9™ trace module for ARM926EJ-S debug
- 16-/18-bit LCD controller with dedicated system DMA channel
- 32kHz Operating System (OS) timer
- Shared peripherals
- Eight general-purpose timers
- Serial Port Interface (SPI)
- Three Universal Asynchronous Receiver/Transmitters (UARTs) (two supporting SIR modes for IrDA)
- Inter-Integrated Circuit (I2C) master and slave interface
- Multimedia Card (MMC) and Secure Digital (SD) interface
- Multichannel buffered serial port
- Up to 64 shared general-purpose I/Os
- 32kHz synchro counter
- Endian conversion unit
- Hardware accelerators for cryptographic functions
- Random number generation
- DES and 3DES
- SHA-1 and MD5
- Individual power-saving modes for MPU/DSP/TC
- On-chip scan-based emulation logic
- IEEE Std 1149.1 (JTAG) boundary-scan logic
- Three 289-ball BGA (Ball Grid Array) packages (ZDY and ZZG - lead-free; GDY - with lead)
Applications
- Applications processing devices
- Mobile communications
- WAN 802.11X
- Bluetooth™
- GSM, GPRS, EDGE
- CDMA
- Video and image processing (MPEG4, JPEG, Windows® Media Video, etc.)
- Advanced speech applications (text-to-speech, speech recognition)
- Audio processing (MPEG-1 Audio Layer3 [MP3], AMR, WMA, AAC, and other GSM speech Codecs)
- Graphics and video acceleration
- Generalized web access
- Data processing
Functional Block Diagram
Inilathala: 2020-07-14
| Na-update: 2024-07-01