CY14V101 1-Mb Quad SPI nvSRAM

Infineon Technologies CY14V101 1-Mbit (128K × 8) Quad SPI nvSRAM couples a 1-Mbit nvSRAM with a QPI interface. The QPI enables the writing and reading of the memory in either a single (one I/O channel for one bit per clock cycle), dual (two I/O channels for two bits per clock cycle), or quad (four I/O channels for four bits per clock cycle) through the use of specific opcodes. The memory in the Infineon Technologies CY14V101 is organized as 128Kbytes, each consisting of SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The SRAM provides infinite read and write cycles, while the nonvolatile cells provide data storage. Data transfers from SRAM to the nonvolatile cells (STORE operation) occur automatically at power-down. Upon power-up, the data is restored to the SRAM from the nonvolatile cells (RECALL operation). Users may also initiate the STORE and RECALL operations through SPI instructions.